RMG nMOS 1^st process enabling 10x lower gate resistivity in N7 bulk FinFETs

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Authors: L.-A. Ragnarsson, H. Dekkers, T. Schram, S. A. Chew, B. Parvais, M. Dehan, K. Devriendt, Z. Tao, F. Sebaai, C. Baerts, S. Van Elshocht, N. Yoshida, A. Phatak, C. Lazik, A. Brand, W. Clark, D. Fried, D. Mocuta, K. Barla, N. Horiguchi, A. V.-Y. Thean

Journal title: 2015 Symposium on VLSI Technology (VLSI Technology)

Journal publisher: IEEE

Published year: 2015

Published pages: T148-T149

DOI identifier: 10.1109/VLSIT.2015.7223656

ISBN: 978-4-86348-501-3