Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer

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Authors: K. Seidel, D. Lehninger, R. Hoffmann, T. Ali, M. Lederer, R. Revello, K. Mertens, K. Biedermann, Y. Shen, D. Wang, M. Landwehr, A. Heinig, T. Kämpfe, H. Mähne, K. Bernert, S. Thiem

Journal title: VLSI Symposium on Technology & Circuits

Journal publisher: IEEE

Published year: 2022

DOI identifier: 10.1109/vlsitechnologyandcir46769.2022.9830141