Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration

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Authors: R. Berthelon, F. Andrieu, P. Perreau, E. Baylac, A. Pofelski, E. Josse, D. Dutartre, A. Claverie, M. Haond

Journal title: 2016 46th European Solid-State Device Research Conference (ESSDERC)

Journal publisher: IEEE

Published year: 2016

Published pages: 127-130

DOI identifier: 10.1109/ESSDERC.2016.7599604

ISBN: 978-1-5090-2969-3