Impact of the design layout on threshold voltage in SiGe channel UTBB-FDSOI pMOSFET

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Authors: R. Berthelon, F. Andrieu, S. Ortolland, R. Nicolas, T. Poiroux, E. Baylac, D. Dutartre, E. Josse, A. Claverie, M. Haond

Journal title: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

Journal publisher: IEEE

Published year: 2016

Published pages: 88-91

DOI identifier: 10.1109/ULIS.2016.7440059

ISBN: 978-1-4673-8609-8