Impact of strain on access resistance in planar and nanowire CMOS devices

This is a publication. If there is no link to the publication on this page, you can try the pre-formated search via the search engines listed on this page.

Authors: R. Berthelon, F. Andneu, F. Triozon, M. Casse, L. Bourdet, G. Ghibaudo, D. Rideau, Y. M. Niquet, S. Barraud, P. Nguyen, C. Le Royer, J. Lacord, C. Tabone, O. Rozeau, D. Dutartre, A. Claverie, E. Josse, F. Arnaud, M. Vinet

Journal title: 2017 Symposium on VLSI Technology

Journal publisher: IEEE

Published year: 2017

Published pages: T224-T225

DOI identifier: 10.23919/VLSIT.2017.7998180

ISBN: 978-4-86348-605-8