Vertically stacked nanowire MOSFETs for sub-10nm nodes: Advanced topography, device, variability, and reliability simulations

This is a publication. If there is no link to the publication on this page, you can try the pre-formated search via the search engines listed on this page.

Authors: M. Karner, O. Baumgartner, Z. Stanojevic, F. Schanovsky, G. Strof, C. Kernstock, H. W. Karner, G. Rzepa, T. Grasset

Journal title: 2016 IEEE International Electron Devices Meeting (IEDM)

Journal publisher: IEEE

Published year: 2016

Published pages: 30.7.1-30.7.4

DOI identifier: 10.1109/IEDM.2016.7838516

ISBN: 978-1-5090-3902-9