Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation

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Authors: F. Andrieu, R. Berthelon, R. Boumchedda, G. Tricaud, L. Brunet, P. Batude, B. Mathieu, E. Avelar, A. Ayres de Sousa, G. Cibrario, O. Rozeau, J. Lacord, O. Billoint, C. Fenouillet-Béranger, S. Guissi, D. Fried, P. Morin, J.P. Noel, B. Giraud, S. Thuries, F. Arnaud, M. Vinet

Journal publisher:  Electron Devices Meeting (IEDM), 2017 IEEE International

Published year: 2017