SiGe HBT / CMOS process thermal budget co-optimization in a 55-nm CMOS node

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Authors: A. Gauthier, P. Chevalier, G. Avenier, G. Ribes, M.-L. Rellier, Y. Campidelli, R. Beneyton, D. Celi, G. Haury, C. Gaquiere

Journal title: 2017 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

Journal publisher: IEEE

Published year: 2017

Published pages: 58-61

DOI identifier: 10.1109/BCTM.2017.8112911

ISBN: 978-1-5090-6383-3